Awesome Contents

Understanding read_csr(mhartid)

Understanding read_csr(mhartid) ⚠ Click here to regain focus ⚠
References ▼
SiFive Developers
Freedom E310-G000 Manual
[1]8:07
RISC-V
User-Level ISA Specification v2.1
[2]13:17[4]39:56
RISC-V
Draft Privileged ISA Specification v1.9.1
[3]26:50
Filter mode:
Topics
asm
hardware
Media
🖌Blackboard
🗪Chat Comment
🖮Programming
📖Research
Credits
Host
Mio Iwakura
Annotator
Matt Mascarenhas
?
?

Keyboard Navigation

Global Keys

W, A, P / S, D, N Jump to previous / next marker
z Toggle filter mode V Revert filter to original state

Menu toggling

q Quotes r References f Filter c Credits

Movement

a
w
s
d
h j k l
←
↑
↓
→

Quotes and References Menus

Enter Jump to timecode

Quotes, References and Credits Menus

o Open URL (in new tab)

Filter Menu

x, Space Toggle category and focus next
X, ShiftSpace Toggle category and focus previous
v Invert topics / media as per focus

Credits Menu

Enter Open URL (in new tab)
0:06Set the stage for the day
0:06Set the stage for the day
0:06Set the stage for the day
0:42Read through plic.h
0:42Read through plic.h
0:42Read through plic.h
2:21Read through encoding.h, where we find read_csr()
2:21Read through encoding.h, where we find read_csr()
2:21Read through encoding.h, where we find read_csr()
6:33Read freedom-e300-hifive1/platform.h
6:33Read freedom-e300-hifive1/platform.h
6:33Read freedom-e300-hifive1/platform.h
8:07Consult the manual: Memory Map, and Interrupts1
8:07Consult the manual: Memory Map, and Interrupts1
8:07Consult the manual: Memory Map, and Interrupts1
11:59Continue reading plic_driver.c with a view to understanding read_csr(mhartid)
11:59Continue reading plic_driver.c with a view to understanding read_csr(mhartid)
11:59Continue reading plic_driver.c with a view to understanding read_csr(mhartid)
13:17Consult the User-Level spec on CSR instructions2
13:17Consult the User-Level spec on CSR instructions2
13:17Consult the User-Level spec on CSR instructions2
19:05Atomic Read and Set Bits in CSR
19:05Atomic Read and Set Bits in CSR
19:05Atomic Read and Set Bits in CSR
26:50Consult the Privileged ISA Spec on CSR 3
26:50Consult the Privileged ISA Spec on CSR 3
26:50Consult the Privileged ISA Spec on CSR 3
30:30Begin to understand the csrr instruction, aided by the table of CSR addresses
30:30Begin to understand the csrr instruction, aided by the table of CSR addresses
30:30Begin to understand the csrr instruction, aided by the table of CSR addresses
34:34Learn that mhartid is the "Hardware thread ID"
34:34Learn that mhartid is the "Hardware thread ID"
34:34Learn that mhartid is the "Hardware thread ID"
39:56Read about the Machine-Level ISA4
39:56Read about the Machine-Level ISA4
39:56Read about the Machine-Level ISA4
45:25insofaras I think the %0 refers to the _tmp variable
45:25insofaras I think the %0 refers to the _tmp variable
45:25insofaras I think the %0 refers to the _tmp variable
45:59insofaras The GCC inline asm syntax is pretty weird
45:59insofaras The GCC inline asm syntax is pretty weird
45:59insofaras The GCC inline asm syntax is pretty weird
46:56Summarise what read_csr(mhartid) is doing
46:56Summarise what read_csr(mhartid) is doing
46:56Summarise what read_csr(mhartid) is doing
47:33Move on to the next line of code
47:33Move on to the next line of code
47:33Move on to the next line of code
50:20The parameters that csrr takes, and what read_csr() and mhartid are
50:20The parameters that csrr takes, and what read_csr() and mhartid are
50:20The parameters that csrr takes, and what read_csr() and mhartid are
53:47Discover what _AC() and PLIC_ENABLE_OFFSET() are
53:47Discover what _AC() and PLIC_ENABLE_OFFSET() are
53:47Discover what _AC() and PLIC_ENABLE_OFFSET() are
56:51Determine to consult the spec tomorrow
56:51Determine to consult the spec tomorrow
56:51Determine to consult the spec tomorrow