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Understanding read_csr(mhartid)
Understanding read_csr(mhartid)
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References ▼
SiFive Developers
Freedom E310-G000 Manual
[1]
8:07
RISC-V
User-Level ISA Specification v2.1
[2]
13:17
[4]
39:56
RISC-V
Draft Privileged ISA Specification v1.9.1
[3]
26:50
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Mio Iwakura
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Matt Mascarenhas
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0:06
Set the stage for the day
0:06
Set the stage for the day
0:06
Set the stage for the day
0:42
Read through plic.h
0:42
Read through plic.h
0:42
Read through plic.h
2:21
Read through encoding.h, where we find read_csr()
2:21
Read through encoding.h, where we find read_csr()
2:21
Read through encoding.h, where we find read_csr()
6:33
Read freedom-e300-hifive1/platform.h
6:33
Read freedom-e300-hifive1/platform.h
6:33
Read freedom-e300-hifive1/platform.h
8:07
Consult the manual: Memory Map, and Interrupts
1
8:07
Consult the manual: Memory Map, and Interrupts
1
8:07
Consult the manual: Memory Map, and Interrupts
1
11:59
Continue reading plic_driver.c with a view to understanding read_csr(mhartid)
11:59
Continue reading plic_driver.c with a view to understanding read_csr(mhartid)
11:59
Continue reading plic_driver.c with a view to understanding read_csr(mhartid)
13:17
Consult the User-Level spec on CSR instructions
2
13:17
Consult the User-Level spec on CSR instructions
2
13:17
Consult the User-Level spec on CSR instructions
2
19:05
Atomic Read and Set Bits in CSR
19:05
Atomic Read and Set Bits in CSR
19:05
Atomic Read and Set Bits in CSR
26:50
Consult the Privileged ISA Spec on CSR
3
26:50
Consult the Privileged ISA Spec on CSR
3
26:50
Consult the Privileged ISA Spec on CSR
3
30:30
Begin to understand the csrr instruction, aided by the table of CSR addresses
30:30
Begin to understand the csrr instruction, aided by the table of CSR addresses
30:30
Begin to understand the csrr instruction, aided by the table of CSR addresses
34:34
Learn that mhartid is the "Hardware thread ID"
34:34
Learn that mhartid is the "Hardware thread ID"
34:34
Learn that mhartid is the "Hardware thread ID"
39:56
Read about the Machine-Level ISA
4
39:56
Read about the Machine-Level ISA
4
39:56
Read about the Machine-Level ISA
4
45:25
insofaras
I think the %0 refers to the _tmp variable
45:25
insofaras
I think the %0 refers to the _tmp variable
45:25
insofaras
I think the %0 refers to the _tmp variable
45:59
insofaras
The GCC inline asm syntax is pretty weird
45:59
insofaras
The GCC inline asm syntax is pretty weird
45:59
insofaras
The GCC inline asm syntax is pretty weird
46:56
Summarise what read_csr(mhartid) is doing
46:56
Summarise what read_csr(mhartid) is doing
46:56
Summarise what read_csr(mhartid) is doing
47:33
Move on to the next line of code
47:33
Move on to the next line of code
47:33
Move on to the next line of code
50:20
The parameters that csrr takes, and what read_csr() and mhartid are
50:20
The parameters that csrr takes, and what read_csr() and mhartid are
50:20
The parameters that csrr takes, and what read_csr() and mhartid are
53:47
Discover what _AC() and PLIC_ENABLE_OFFSET() are
53:47
Discover what _AC() and PLIC_ENABLE_OFFSET() are
53:47
Discover what _AC() and PLIC_ENABLE_OFFSET() are
56:51
Determine to consult the spec tomorrow
56:51
Determine to consult the spec tomorrow
56:51
Determine to consult the spec tomorrow